 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| INTEGRATED CIRCUITS DATA SHEET SAA7206H DVB compliant descrambler Product specification Supersedes data of 1996 Oct 02 File under Integrated Circuits, IC02 1996 Oct 09 Philips Semiconductors Product specification DVB compliant descrambler CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8 9 10 11 12 13 14 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.4 15 16 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION MPEG-2 systems parsing PES level descrambling Descrambler core Microcontroller interface Output interfacing Boundary scan test Programming the descrambler LIMITING VALUES HANDLING THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering QFP SO Method (QFP and SO) Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS SAA7206H 1996 Oct 09 2 Philips Semiconductors Product specification DVB compliant descrambler 1 FEATURES SAA7206H * Descrambler, based on the super descrambler mechanism algorithm with stream decipher and block decipher. The descrambler is initialized with a 64-bit Control Word (CW) at the beginning of a transport stream packet payload of a selected Packet Identification (PID). The descrambler operates on transport stream packet or Packetized Elementary Stream (PES) packet payloads * Microcontroller support; only for control, no specific descrambling tasks are performed by the microcontroller. However, parsing and processing of conditional access information (such as EMM and ECM data) is left to the system microcontroller * Boundary scan test port for boundary scan. 2 GENERAL DESCRIPTION * Input data fully compliant with the Transport Stream (TS) definition of the MPEG-2 systems specification * Input data signals; [Forward Error Correction (FEC) Interface] - modem data input bus (8-bit wide) - valid input data indicator - erroneous packet indicator - first packet byte indicator - byte strobe signal (for asynchronous mode only). The interface can be programmed to one of two modes: - Asynchronous mode; byte strobe input signal (MBCLK) < 9 MHz, for connection to a modem (FEC) - Synchronous mode; MBCLK is not used. Data is delivered to the descrambler synchronized with the chip clock (DCLK) [9 MHz (typ.) with a 33% duty cycle]. * No external memory * Effective bit rate; fbit 72 MHz * Control interface; 8-bit multiplexed data/address, memory mapped I/O (90CE201 microcontroller parallel bus compatible), in combination with a microcontroller interrupt signal (IRQ) * Output ports are identical to the input data interface (demultiplexer interface) - except for the packet error indicator (MB/MB), as the descrambler translates an active MB signal to the `transport_error_indicator' bit in the transport stream - except for the byte strobe input signal (MBCLK), as data is delivered to the demultiplexer, synchronized with the descrambler chip clock which is generated by the demultiplexer 3 ORDERING INFORMATION The SAA7206H (DVB compliant) is designed for use in MPEG-2 based digital TV receivers, incorporating conditional access filters. Such receivers are to be implemented in, for instance, a digital video broadcasting top set box, or an integrated digital TV receiver. An example of a demultiplexer/descrambler system configuration, containing a channel decoder module, a demultiplexer, a system controller and a conditional access system is shown in Fig.3. The main function of the descrambler is to descramble the payloads of MPEG-2 TS packets or PES packets. In addition, the descrambler retrieves Conditional Access (CA) data [such as Entitlement Management Messages (EMM) and Entitlement Control Messages (ECM) etc.] from the stream and passes it to the system microcontroller for processing. PACKAGE TYPE NUMBER NAME SAA7206H QFP64 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm VERSION SOT319-2 1996 Oct 09 3 Philips Semiconductors Product specification DVB compliant descrambler 4 QUICK REFERENCE DATA SYMBOL VDDD VDDD(core) Ptot fclk Tamb 5 PARAMETER digital supply voltage digital supply voltage for core total power dissipation clock frequency operating ambient temperature VDDD(core) = 3.3 V, VDDD = 5 V, CL = 15 pF duty cycle = 30 to 55% CONDITIONS - - - - 0 MIN. - - - - - TYP. SAA7206H MAX. 5.5 3.6 250 9 70 V V UNIT mW MHz C BLOCK DIAGRAM handbook, full pagewidth TC1 61 TC0 60 MIN7 to MIN0 47 to 50, 53 to 56 MB/MB MBCLK MDV MSYNC 44 45 43 59 TDI TCK TMS TRST 18 19 20 46 TEST CONTROL BLOCK FOR BOUNDARY SCAN TEST AND SCAN TEST TRANSPORT STREAMS AND AF PARSER 22 DCLK 62 POR TDO DAT7 to DAT0 DCS R/W A1 A0 IRQ 37 SAA7206 PACKET IDENTIFICATION BANK CONTROL WORD BANK 7 to 9, 12 to 16 3 63 4 5 1 MICROCONTROLLER INTERFACE STREAM DECIPHER BLOCK DECIPHER CONDITIONAL ACCESS FILTERS 40 24, 25, 28 to 31, 34, 35 OUTPUT INTERFACE 2, 17, 23, 27, 33, 52, 58 38 39 OE DATO0 to DATO7 DVO SYNCO VDDD(core) VDDD1 to VDDD9 36 6, 11, 21, 26, 32, 41, 51, 57, 64 10, 42 MGG313 VSSD1 to VSSD7 VSSD1(core), VSSD2(core) Fig.1 Block diagram. 1996 Oct 09 4 Philips Semiconductors Product specification DVB compliant descrambler 6 PINNING SYMBOL IRQ VSSD1 DCS A1 A0 VDDD1 DAT7 DAT6 DAT5 VSSD1(core) VDDD2 DAT4 DAT3 DAT2 DAT1 DAT0 VSSD2 TDI TCK TMS VDDD3 DCLK VSSD3 DATO0 DATO1 VDDD4 VSSD4 DATO2 DATO3 DATO4 DATO5 VDDD5 VSSD5 DATO6 DATO7 VDDD(core) TDO DVO SYNCO PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 I/O O GND I I I supply I/O I/O I/O GND supply I/O I/O I/O I/O I/O GND I I I supply I GND O O supply GND O O O O supply GND O O supply O O O digital ground 1 descrambler chip select input (active LOW) A1 = address/data indicator input A0 = MSByte indicator input digital supply voltage 1 (+5 V) microcontroller bidirectional data bus bit 7 microcontroller bidirectional data bus bit 6 microcontroller bidirectional data bus bit 5 digital ground 1 for core digital supply voltage 2 (+5 V) microcontroller bidirectional data bus bit 4 microcontroller bidirectional data bus bit 3 microcontroller bidirectional data bus bit 2 microcontroller bidirectional data bus bit 1 microcontroller bidirectional data bus bit 0 digital ground 2 boundary scan test data input boundary scan test clock input boundary scan test mode select input digital supply voltage 3 (+5 V) DESCRIPTION SAA7206H interrupt request output for microcontroller (active LOW, open-drain output) 9 MHz descrambler chip clock input (duty cycle range: 30 to 55%) digital ground 3 data output to demultiplexer bit 0 data output to demultiplexer bit 1 digital supply voltage 4 (+5 V) digital ground 4 data output to demultiplexer bit 2 data output to demultiplexer bit 3 data output to demultiplexer bit 4 data output to demultiplexer bit 5 digital supply voltage 5 (+5 V) digital ground 5 data output to demultiplexer bit 6 data output to demultiplexer bit 7 digital supply voltage for core (+3.3 V) boundary scan test data output valid output data indicator indicates the first output byte (sync) of a transport packet 1996 Oct 09 5 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H SYMBOL OE VDDD6 VSSD2(core) MSYNC MDV MB/MB TRST MIN7 MIN6 MIN5 MIN4 VDDD7 VSSD6 MIN3 MIN2 MIN1 MIN0 VDDD8 VSSD7 MBCLK TC0 TC1 POR R/W VDDD9 PIN 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I/O I supply GND I I I I I I I I supply GND I I I I supply GND I I I I I supply DESCRIPTION output enable (active LOW), if HIGH, device outputs are high impedance, (connected to logic 0 in normal operation) digital supply voltage 6 (+5 V) digital ground 2 for core indicates the first input byte (sync) of a transport packet valid input data indicator packet error indicator input (programmable polarity) boundary scan reset input (LOW in normal operation) 8-bit wide modem data input bit 7 8-bit wide modem data input bit 6 8-bit wide modem data input bit 5 8-bit wide modem data input bit 4 digital supply voltage 7 (+5 V) digital ground 6 8-bit wide modem data input bit 3 8-bit wide modem data input bit 2 8-bit wide modem data input bit 1 8-bit wide modem data input bit 0 digital supply voltage 8 (+5 V) digital ground 7 byte strobe input signal < 9 MHz test control input 0 (not connected in normal operation) test control input 1 (not connected in normal operation) power-on reset, must be active HIGH during at least 5 DCLK pulses read/write input selection digital supply voltage 9 (+5 V) 1996 Oct 09 6 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H 59 MBCLK 64 VDDD9 57 VDDD8 58 VSSD7 56 MIN0 55 MIN1 54 MIN2 53 MIN3 handbook, full pagewidth 52 VSSD6 51 VDDD7 50 MIN4 49 MIN5 48 MIN6 47 MIN7 46 TRST 45 MB/MB 44 MDV 43 MSYNC 42 VSSD2(core) 41 VDDD6 40 OE 39 SYNCO 38 DVO 37 TDO 36 VDDD(core) 35 DATO7 34 DATO6 33 VSSD5 VDDD5 32 MGG312 62 POR 63 R/W 61 TC1 IRQ VSSD1 DCS A1 A0 VDDD1 DAT7 DAT6 DAT5 1 2 3 4 5 6 7 8 9 60 TC0 DATO0 24 VSSD1(core) 10 VDDD2 11 DAT4 12 DAT3 13 DAT2 14 DAT1 15 DAT0 16 VSSD2 17 TDI 18 TCK 19 TMS 20 VDDD3 21 DCLK 22 VSSD3 23 SAA7206 DATO1 25 VDDD4 26 VSSD4 27 DATO2 28 DATO3 29 DATO4 30 Fig.2 Pin configuration. 1996 Oct 09 7 DATO5 31 Philips Semiconductors Product specification DVB compliant descrambler 7 FUNCTIONAL DESCRIPTION SAA7206H * The CA filters select data on the basis of PIDs, and a combination of MPEG-2 section addressing fields. Selected CA data is stored in eighteen 256 byte (constrained random access) buffers which can be read by the microcontroller. The CA message section has a maximum length of 256 bytes. It consists of a 3 bytes long header with Table_id and section_length data. The remaining part of the CA message are the CA_data_bytes (see Fig.4). If a section is longer than 256 bytes, the data capture is stopped (with an interrupt to the microcontroller) after 256 bytes are in the buffer and the `section_to_long' bit is set. The filters are capable of monitoring 18 CA streams (containing EMM and ECM data) simultaneously. Two different lengths are used for address filtering: - 16 filters where the first 7 bytes of the CA_data_bytes field are used for address filtering - 2 (DVB compliant) filters where the first 17 bytes of the CA_data_bytes field are used for address filtering - A chip identification byte (value 0x02) can be read by the software from address 0x0003 (see Table 10). A block diagram of the internal structure of the descrambler (DVB compliant) is illustrated in Fig.1. The block diagram illustrates the main functional modules in the descrambler. The modules are as follows: * The MPEG-2 syntax parser, which parses transport streams that comply with the MPEG-2 systems specification * The descrambler module consisting of: - A Packet Identification (PID) bank containing 6 PID values of the streams selected for descrambling. All bits of PID5 (address 0x0205) can be masked individually with PID5_mask (address 0x0209), to enable multiple PID selection. - A Control Word (CW) bank containing 6 CW pairs and a default CW. A CW pair consists of 2 descrambler control words (odd and even), each word with a length of 64 bits. - The descrambler core containing the actual descrambler with the stream cipher and the block cipher module. * A microcontroller interface providing protocol handling for the memory mapped I/O control bus (Philips 90CE201 compatible). This module contains an interrupt request handler and data filters for the retrieval of Conditional Access (CA) information: handbook, full pagewidth CONDITIONAL ACCESS SYSTEM MICROCONTROLLER DEMODULATOR AND FORWARD ERROR CORRECTOR DVB DESCRAMBLER (SAA7206H) DEMULTIPLEXER (SAA7205) MGG314 Fig.3 Demultiplexer system configuration. 1996 Oct 09 8 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H handbook, full pagewidth 7 or 17 bytes of filtering CA_data_bytes [253 bytes (max.)] section payload [253 bytes (max.)] table_id reserved section length byte 0 byte 1 section header (3 bytes) MGG316 Fig.4 Syntax of the conditional access message. Table 1 Explanation of Fig.4 DESCRIPTION 8-bit field for identification 4-bit field with section_syntax_indicator (1 bit), DVB_reserved (1 bit) and ISO_reserved (2 bits) 12-bit field that specifies the number of bytes that follow the section_length field up to the end of the section 8-bit field that carries private CA information. Up to the first 17 CA_data_bytes may be used for address filtering SYNTAX Table_id Reserved Section_length CA_data_byte 1996 Oct 09 9 Philips Semiconductors Product specification DVB compliant descrambler 7.1 MPEG-2 systems parsing SAA7206H The hierarchical multiplex level below the MPEG-2 transport stream is the packetized elementary stream. The PES header is only parsed partially by the DVB descrambler to locate its scrambling control bits. Parsing is performed for all incoming transport packets, and the parser is synchronized to a rising edge on its MSYNC input. A microcontroller can compose a set of 6 PIDs by programming the appropriate registers in the PID filter bank within the descrambler. These PIDs identify the packets of the streams that are to be descrambled. All 13 bits of PID5 (see Table 10, address 0x0205) can be individually enabled/disabled with a mask of 13 bits (see Table 10, address 0x0209) to enable multiple PID selection. The PIDs of PES scrambled packets must be indicated by programming a logic 1 to the corresponding bit of the `PIDi_is_pes' word (see Table 10, address 0x0206). MPEG-2 multiplex fields which are related to CA information, in so called sections, are parsed only partly. CA sections containing for instance Entitlement Management Messages (EMM) and Entitlement Control Messages (ECM) etc. are retrieved from the stream and stored in 256 byte buffers in the CA filter module. For the selection of CA data, 18 additional PIDs and section header information (table_id, address field, both with bit masks) can be programmed. All 13 bits of PID filters 16 and 17 can be individually enabled/disabled with a mask of 13 bits (see Table 10, addresses 0x03A6 and 0x03BA) to enable multiple PID selection for CA messages. A microcontroller may access data in the 256 byte CA buffers (each filter has its own buffer thus 18 in total) for software based parsing and processing. The descrambler receives data from a Forward Error Correction (FEC) decoder (see Fig.5) in a digital TV receiver, in the following input data format: * 8 data bits via MIN7 to MIN0. * A valid input data indicator signal (MDV), which is HIGH for consecutive valid bytes and output by either a FEC decoder or a descrambler. Consequently the descrambler input data is allowed to have a `bursty' nature. * A transport packet error indicator (MB/MB) which is HIGH for the duration of each 188 byte transport packet in which the FEC decoder found more errors than it could correct. The polarity (active HIGH or LOW) of the error indicator is programmable [bit `Bad_polarity' (see Table 10, address 0x0100)]. * A packet sync signal (MSYNC) which goes HIGH at the start of the first byte of a transport packet. Only the rising edge of MSYNC is used for synchronization, the exact HIGH time of the signal is therefore irrelevant. * A byte strobe signal (MBCLK; < 9 MHz) which indicates consecutive data bytes in the input stream, in the non 9 MHz mode only [bit `9 MHz_interface' = 0 (see Table 10, address 0x0100)]. MBCLK is used as an enable signal, and transport stream input bytes are sampled on its rising edges. If the input interface is programmed to the 9 MHz mode (`9 MHz_interface' = 1), the MBCLK signal is ignored and bytes are latched on rising edges of the DCLK. * A descrambler clock signal (DCLK; 9 MHz; duty cycle range 30 to 55%) which is the processing clock for the descrambler IC. If rising edges of this signal are used to input data to the descrambler, the 9 MHz mode must be programmed (bit `9 MHz_interface' = 1, see Table 10, address 0x0100). The parser module in the descrambler parses transport streams compliant to the MPEG-2 systems syntax. MPEG-2 systems specifies a hierarchical two-level multiplex (see Fig.6). The top hierarchical level is the transport stream, consisting of relatively short (188 byte) transport packets. Each transport packet consists of a 4 byte transport header, an optional adaptation field and a payload. The transport header contains a 13-bit PID field. The adaptation field may contain Program Clock Reference (PCR) data and transport private data, among others. Both transport header and optional adaptation fields are parsed by the TS parser module. 1996 Oct 09 10 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H handbook, full pagewidth 8 MIN7 to MIN0 MBCLK FEC MDV MB/MB MSYNC DESCRAMBLER DCLK MBCLK MIN7 to MIN0 message invalid data message invalid data MSYNC MDV MB/MB error-free transport packet (programmable polarity) MB/MB erroneous transport packet MGG317 Fig.5 Signal constellation FEC decoder - descrambler Interfacing. handbook, full pagewidth transport stream packetized elementary stream elementary stream MGG318 = transport_header = pes_header = stuffing Fig.6 MPEG-2 two level hierarchical demultiplexing. 1996 Oct 09 11 Philips Semiconductors Product specification DVB compliant descrambler 7.2 PES level descrambling 7.3 Descrambler core SAA7206H PES level descrambling is possible in accordance with the recommendations of the DVB standard with the DVB descrambler IC. The actual restrictions however, required by the DVB descrambler IC, are less strict than to the recommendations in the DVB standard. The restrictions for PES level descrambling imposed by the IC are as follows: * Scrambling shall only occur at one level (TS or PES) and is not allowed to occur at both levels simultaneously * The complete PES header must be present in exactly one TS packet. Consequently, the size of a PES packet header shall not exceed 184 bytes * Only the PES packet data bytes (PES payload) are descrambled * TS packets resulting from scrambling at PES level are not chained and thus are independent. Consequently, the internal descrambler algorithms (stream decipher and block decipher) are initialized at the start of each (PES scrambled) TS packet payload. In order to be able to distinguish between sections and PES packets, a PID for a PES scrambled packet is indicated by programming the according `PIDi_is_pes' bit (see Table 10, address 0x0206) to logic 1. If the payload_unit_start_indicator bit is set in the TS packet header and the `PIDi_is_pes' bit is set for a particular PID, the PES scrambling control bits, which are present in the PES header, are stored in the accessible `pes_sc_PIDi' register (see Table 10, address 0x0208). Descrambling at TS level always has priority over descrambling at PES level. Consequently, PES level descrambling is only possible when the transport_scrambling_control bits in the TS header are `00'. In that situation the payload of the PES packets is descrambled using the scrambling control bits of the `pes_sc_PIDi' register. Remark: PID masking (for PID5) should not be combined with PES level descrambling. Only one pair of PES scrambling control bits per PID is stored in an Internal register. Thus interleaving of PES messages, which can occur in the situation of multiple PID selection, can give the wrong descrambling result. As a consequence the microcontroller must program the `PID5_is_pes' bit (see Table 10, address 0x0206) to logic 0 when multiple PID selection is used. The descrambler core consists of three modules: * A PID filter which selects packets for descrambling * A control word bank containing 6 sets (odd and even) of control words and a Default Control Word (DCW) * The super descrambler core with the implementation of the stream decipherment and the block decipherment algorithms. The PID filter contains 6 registers which hold data in the format indicated in Fig.7. Six individual PIDs are stored to identify 6 packet streams. All bits of PID5 (see Table 10, address 0x0205) can be masked with the `PID5_mask' (see Table 10, address 0x209), to enable descrambling on multiple PIDs. To disable a bit of PID5 with the `PID5_mask' a logic 0 must be programmed. After a power-on reset pulse all mask bits are preset to logic 1. To each PID a 3-bit Control Word Pair Index pointer (CWPI) is attached. A CWPI prescribes which control word pair, consisting of odd and even control words, has to be used to initialize the DVB descrambler for payloads of packets with the associated PID. After a power-on reset all CWPIs are set to `111' to enable a correct initialization of the conditional access system. If two or more programmed PIDs match the PID of the TS packet at the same time (while the CWPI value of the programmed PIDs is not equal to `110' or `111'), the programmed PID with the lower index number has a higher priority. However, the default control word, when enabled, has the highest priority. Thus, the built-in priority (HIGH-to-LOW transition) for the programmed PIDs is; DCW, PID0, PID1, PID2, PID3, PID4 and PID5. A 2-bit scrambling_control field is present in the TS packet header and in the PES header (ts_sc1 and ts_sc0 and pes_sc1 and pes_sc0 respectively). The bits in this header field indicate whether the TS packet or PES payload is scrambled or not. In addition, these bits also indicate which control word (odd or even) of a control word pair was used to initialize the DVB descrambler, as indicated in Tables 2 and 3. 1996 Oct 09 12 Philips Semiconductors Product specification DVB compliant descrambler If the payload of a packet is descrambled, the descrambler subsequently resets the scrambling_control bits in the TS or PES header (to `00'). For each of the 6 PIDs in the PID filter bank the values of the TS scrambling_control bits are stored in a microcontroller accessible register, prior to descrambling [bits: `ts_sc_PIDi1' and `ts_sc_PIDi0'; (see Table 10, address 0x0208), `i' is in the range 5 to 0]. For each of the 6 PIDs in the PID filter bank, of which the corresponding PIDi_is_pes bit (see Table 10, address 0x0206) is also set to logic 1, the values of the PES scrambling_control bits are stored in a microcontroller accessible register, prior to descrambling [bits:`pes_sc_PIDi1' and `pes_sc_PIDi0' (see Table 10, address 0x0208) `i' is in the range 5 to 0]. TS and PES scrambling_control retrieval is independent of the value of the CWPI. Table 2 Definition of the bits in the PES scrambling_control field DESCRIPTION data is not scrambled data is not scrambled data is scrambled with the EVEN control word data is scrambled with the ODD control word Definition of the bits in the TS scrambling_control field DESCRIPTION data is not scrambled data is scrambled with the default control word data is scrambled with the EVEN control word data is scrambled with the ODD control word SAA7206H Remark: The payloads of packets with TS scrambling_control bits equal to `01' are descrambled using the default control word, regardless of their PID and/or CWPI values. Thus, even PIDs which are not programmed in the PID filter bank are descrambled with the DCW should transport_scrambling_control = `01'. For PIDs in the PID filter bank, if transport_scrambling_control = `01', the payload is descrambled with the default control word, regardless of the value of the associated CWPI. If the default CW is invalid however [`DCW_valid' = 0 (see Table 10, address 0x0206)], DCW based descrambling is disabled. Descrambling using the DCW is only possible on TS packet level. The control word bank contains storage space for 6 control word pairs and a default control word. A control word pair consists of 2 CWs and an odd and even CW, as indicated in Table 4. A control word contains 64 bits. In conjunction with the control word selection mechanism given in Table 4, the CW bank allows any CW pair to be used with any PID. All PIDs may, therefore, use their own specific CW pair, but all of them may also share one CW pair. The super descrambler algorithm is implemented in the core of the descrambler. Descrambling is performed on the payload of a transport packet or a PES. The transport header, the (optional) adaptation field and the PES header are excepted. VALUE 00 01 10 11 Table 3 VALUE 00 01 10 11 1996 Oct 09 13 Philips Semiconductors Product specification DVB compliant descrambler Table 4 Descrambler control word storage; see Table 10 CONTROL WORD (128 BITS) Control word 0 odd Control word 1 odd Control word 2 odd Control word 3 odd Control word 4 odd Control word 5 odd Default control word Control word 0 even Control word 1 even Control word 2 even Control word 3 even Control word 4 even Control word 5 even - SAA7206H ADDRESS 0x1000 to 0x1007 0x1008 to 0x100F 0x1010 to 0x1017 0x1018 to 0x101F 0x1020 to 0x1027 0x1028 to 0x102F 0x1030 to 0x1033 handbook, full pagewidth 15 PID_0 32 CWPI_0 0 0x0200 - W PID_5 15 76 CWPI_5 21 PID5_is_pes to PID0_is_pes 0 0x0205 - W DCW_valid 0x0206 - W 15 12 11 ts_sc_PID5[1..0] to ts_sc_PID0[1..0] 0x0207 - R 15 12 11 pes_sc_PID5[1..0] to pes_sc_PID0[1..0] 0x0208 - R 15 13 12 PID5_mask MGG319 0x0209 - W See Table 10 for details. Fig.7 Syntax and definition of PID and control word pair Index. Table 5 CWPI values; see Fig.7 CWPI VALUE 000 001 010 011 100 101 110 111 DESCRIPTION select control word pair 0 select control word pair 1 select control word pair 2 select control word pair 3 select control word pair 4 select control word pair 5 DO NOT descramble DO NOT descramble 14 1996 Oct 09 Philips Semiconductors Product specification DVB compliant descrambler 7.4 Microcontroller interface 0x0002/0x0004 handbook, halfpage (read only) 19-bit status SAA7206H The microcontroller interface provides a means of communication between a system controller (for instance "Philips 90CE201") in a digital TV receiver and the descrambler internal registers and buffers. The physical interface consists of: * DAT7 to DAT0; an 8-bit wide bidirectional data bus. Data and address information are multiplexed on this bus. * DCS; an active LOW chip select signal. The descrambler only responds to microcontroller communication if this signal is driven LOW. * R/W; an active HIGH read signal, indicating that the microcontroller is attempting to read data from registers or buffers inside the descrambler. If this signal is LOW, data is being written to registers or buffers inside the descrambler. * A1 and A0; a 2-bit address bus. If the least significant address bit (0) is logic 0, the most significant byte of a 16-bit register is addressed, otherwise the least significant byte is selected. If the most significant address bit (1) is logic 1 DAT7 to DAT0 carries the address information, otherwise it will carry control data. * IRQ; an active LOW (open-drain output) interrupt request signal. An interrupt is set if one of the15 bits in the descramblers internal interrupt register is set. The interrupt mechanism consists of three 15-bit registers and one 4-bit register, as illustrated in Fig.8. The interrupt status register enables the microcontroller to monitor the momentary status of the interrupts. This is particularly useful during read operations in the descramblers CA buffers, as the interrupt status bits in question [`flt0_stat', `flt1_stat', etc. (see Table 10, addresses 0x0002 and 0x0004)] are reset when the buffers have been emptied or released. The interrupt mask register (see Table 10, address 0x0001) prevents individual interrupts from resetting IRQ (to logic 0). The interrupt status bits are logically ANDed with the mask. If a rising edge occurs on one of the resulting signals, it is latched into the interrupt register, thus resetting IRQ. momentary status of the individual interrupt bits 0x0001 (write only) 15-bit mask enables/disables individual interrupts 0x0000 (read/write) 15-bit interrupt latched interrupts, indicating which interrupt(s) set IRQ IRQ MGG320 The interrupt register is reset when addressed. Fig.8 Descrambler version 3, microcontroller interrupt mechanism. Table 6 Definition of interrupt mechanism; see Fig.8 MEANING OF INTERRUPT filter 0 retrieved CA data filter 1 retrieved CA data filter 2 retrieved CA data filter 3 retrieved CA data filter 4 retrieved CA data filter 5 retrieved CA data filter 6 retrieved CA data filter 7 retrieved CA data filter 8 retrieved CA data filter 9 retrieved CA data filter 10 retrieved CA data filter 11 retrieved CA data filter 12 retrieved CA data filter 13 retrieved CA data filter 14, 15, 16 or 17 retrieved CA data empty BIT NUMBER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1996 Oct 09 15 Philips Semiconductors Product specification DVB compliant descrambler The interrupt register itself is reset (to 0000000000000000) as soon as it is addressed (0x0000) by the microcontroller. A typical example of communication between microcontroller and descrambler is illustrated in Fig.9. The descrambler contains an auto increment address counter which can be loaded by performing a write address operation. The present operation, whether read or write, is now performed on the current address. The next operation, whether read or write, is performed on the current address plus 1. Remark: Avoid resetting the auto increment address counter to 0x0000, when not handling interrupts, as addressing it causes the interrupt register to be reset. Consequently, interrupt information might be lost. The descrambler internal register and buffer addresses are organized as illustrated in Fig.10. The first 4 address bits (15 to 12) are used to select either the descrambler registers (equals 0) or one of the descrambler buffers (ranges 1 and 2). SAA7206H In the buffer mode, the remaining address bits (11 to 0) are part of the word address (range depending on the buffer, see Table 10). In the register mode, bits 11 to 8 specify the register unit number (see Fig.10). The remaining 8 bits of the address (7 to 0) indicate specific register addresses within a selected unit. The address range in a specific register unit depends on the number of registers present and is different for each unit. For details refer to Table 10. The CA filter module in the microcontroller interface unit is capable of accessing general CA messages (ECM and EMM, etc.) in the transport stream. The CA filter module consists of 18 filters and 18 buffers of 256 bytes each, thus each filter has its own data buffer. The 18 filters are divided into two types of filters, which are specified in Table 9. For each filter the `table_id' of the section (the first byte of the section see Fig.9), can be masked. The architecture of the 9 CA filter pairs is shown in Fig.11. handbook, full pagewidth A1 A0 R/W >24 ns DCS DAT7 to DAT0 MSByte LSByte >666 ns MSByte LSByte >666 ns MSByte LSByte write address N read data @ N write data @ N+1 MGG321 The descrambler internal register address is incremented automatically. Fig.9 Microcontroller descrambler communication (example). 1996 Oct 09 16 Philips Semiconductors Product specification DVB compliant descrambler Table 7 (1) SAA7206H Buffer contents BUFFER CONTENTS CW bank CA data buffers for filters 0 to 15 CA data buffers for filters 16 and 17 BUFFER NUMBER handbook, halfpage if 0, registers are addressed, if >0, buffers are addressed register unit number, range 0 to 3 individual register addresses, range depending on the unit number 1 2 3 (2) Table 8 Unit contents UNIT CONTENTS interrupt request handling control parser input control PID filter bank control CA filtering control 0xHHHH MGG322 REGISTER UNIT NUMBER 0 1 2 3 (1) See Table 7. (2) See Table 8. Fig.10 Descrambler, register organization (see Table 10). Table 9 Specification of the number of CA_data_bytes which can be used for address filtering in the three types of filters in the CA filter module (all bits in the filter can be masked individually) NUMBER OF FILTERS 16 2 FILTER LENGTH (BYTES) 7 17 PID MASKABLE no yes FILTER NUMBER Filters 0 to 15 Filters 16 and 17 (DVB compliant) The filter consists of 18 section detectors. Each section detector selects and retrieves section data for CA_messages on the basis of: * PID; which is maskable only for filters 16 and 17 * Table_id; which is maskable for all filters * For filters 0 to 15; the first 7 bytes in the section payload, which are maskable for all filters (see Fig.4) * For filters 16 and 17; the first 17 bytes in the section payload, which are maskable * For all filters (see Fig.4). The CA data detected by a certain filter is stored in the 256 byte buffer, only if its buffer is empty. As soon as an entire section of CA data is stored, an interrupt is generated (see Table 10, address 0x0000). The 18 section detectors can be separately enabled, to avoid unnecessary interrupts. The `filter fired' registers enable the microcontroller to track which filter caused a buffer to be loaded (see Table 10, addresses 0x0300 and 0x0301). The maximum section length of a conditional access message is 256 bytes. If the section length of a message is higher, data acquisition into the buffer is stopped after 256 bytes and an interrupt signal (plus filter fired signal) is generated as normal. In this (erroneous) situation the `section_to_long' bit of the filter is also set, which can be read by the microcontroller (see Table 10). The CA filters allow retrieval of multiple consecutive CA messages, even if these messages have identical selection criteria. For this purpose the 18 filters are grouped in 9 filter pairs (0 and 1, 2 and 3 to 16 and 17). Each of the CA filters in a pair can be programmed equivalently. To prevent two filters from firing at the same time the `equal conditions' bits of the appropriate filter pair can be programmed to logic 1. As a result, the filter with the even (equals lowest) index number (for instance filter_8 of filter pair 8 and 9) fires at the first occurrence of a matching section. If, at the time of the second occurrence of a matching section, the buffer of the filter with the even index number is still occupied, the other filter (with odd index number) of a filter pair fires, thus storing the section data in its buffer. 1996 Oct 09 17 Philips Semiconductors Product specification DVB compliant descrambler If the microcontroller decides to read data from one of the CA buffers (see Table 10, address range filter_0: 0x2000 to 0x207F to filter_17: 0x2880 to 0x28FF) it can determine when to stop reading in two ways. It can periodically poll the `flt0_stat' to `flt17_stat' bits in the interrupt status register (see Table 10, address 0x0002 and 0x0004). Each of these bits goes LOW as soon as the last valid section data is read from the associated CA buffer. Another possibility is to read the `high_flt_address' word (`haddr7 to 0', Table 10, addresses 0x0302 to 0x0313). The high address indicates the number of valid section words (1 word = 2 bytes) that were written into the buffer. This number equals the number of read cycles that has to be performed to retrieve all valid data from the buffer. If the buffer contents have to be removed without being read, the microcontroller can write a logic 1 to the `rst_bf17-0' bit (see Table 10, address 0x0314 and 0x0315) thus releasing the buffer. Another possibility is to perform a write address operation with a value of haddr7 to haddr0 plus buffer base address. The internal auto increment address counter is thus set to the last word in the buffer, causing the interrupt status bit to be reset and the filters to be reactivated, after having been idle during buffer emptying. If, during the acquisition of a CA message, one of the TS packets composing a message contains an error (`transport_error_indicator' = `1') the erroneous TS packet is removed and CA message acquisition is restarted. Thus the complete CA message is lost when at least one of the TS packets which composes this message contains an error. Duplicate TS packets containing CA messages are also removed. 7.5 Output interfacing SAA7206H The output data stream consists of a sequence of bytes. A new byte is present at the data output pins DATO7 to DATO0 at each rising edge of the descrambler chip clock DCLK. The control signals SYNCO and DVO are a delayed (9 MHz) version of the input interface signals MSYNC and MDV respectively. By this form of delay correction the relationship between the data and control signals is maintained. The MB/MB and MBCLK signals are not output to the demultiplexer. The descrambler converts the MB/MB signal to the transport_error_indicator bit in the TS packets. At the descrambler output all information is consequently contained in the stream. MBCLK is only used to clock data into the descrambler, interfacing to the demultiplexer is performed using the 9 MHz DCLK, which is generated by the demultiplexer. 7.6 Boundary scan test The DVB compliant descrambler is equipped with a 5-pins test port interface for Boundary Scan Test (BST). The implementation is in accordance with the BST standard. 1996 Oct 09 18 1996 Oct 09 handbook, full pagewidth Philips Semiconductors CA module structure CA filter pair architecture FILTER 0 PID r equal conditions interrupt to microcontroller INPUT STREAM PID s table_id z address d table_id y address c DVB compliant descrambler 256B BUFFER_0 equal conditions FILTER 1 256B BUFFER_1 CA BUFFER (256 bytes) 19 = filter fired indicator = filter enable identical filter (pairs) 2 to15 FILTER 16 256B BUFFER_16 interrupt to microcontroller equal conditions CA BUFFER (256 bytes) MGG323 FILTER 17 256B BUFFER_17 Product specification SAA7206H Fig.11 CA two filter architecture. 7.7 Programming the descrambler Table 10 Descrambler programming. BITS 15/7 flt14-17_irp flt6_irp msk14 msk6 flt14-17_stat flt6_stat - 0 - - flt17_stat - - - - - - pid8 pid0 pid8 pid0 pid9 pid1 pid9 pid1 pid10 pid2 pid10 pid2 pid9 pid1 pid9 pid1 pid8 pid0 pid8 pid0 pid8 pid0 pid8 pid0 - - - - pid7 cwpi2 pid7 cwpi2 pid7 cwpi2 pid7 cwpi2 pid7 cwpi2 pid7 cwpi2 - - flt16_stat - - - - - - pid11 pid3 pid11 pid3 pid11 pid3 pid11 pid3 pid11 pid3 pid11 pid3 pid10 pid2 pid2 pid10 pid2 pid10 pid9 pid1 pid2 pid1 pid10 pid9 - - - - - - - - - - - - - - - - - - 0 0 0 0 1 - flt15_stat - - - bad_ polarity - - pid6 cwpi1 pid6 cwpi1 pid6 cwpi1 pid6 cwpi1 pid6 cwpi1 pid6 cwpi1 - - - - - flt5_stat flt4_stat flt3_stat flt2_stat flt1_stat flt13_stat flt12_stat flt11_stat flt10_stat flt9_stat msk5 msk4 msk3 msk2 msk1 msk0 flt8_stat flt0_stat - 1 - flt14_stat - - - 9 MHz_ interface - - pid5 cwpi0 pid5 cwpi0 pid5 cwpi0 pid5 cwpi0 pid5 cwpi0 pid5 cwpi0 msk13 msk12 msk11 msk10 msk9 msk8 flt5_irp flt4_irp flt3_irp flt2_irp flt1_irpt flt0_irpt - msk7 - - 0 - - - - - - - - pid12 pid4 pid12 pid4 pid12 pid4 pid12 pid4 pid12 pid4 pid12 pid4 flt13_irp flt12_irp flt11_irp flt10_irp flt9_irp flt8_irp 14/6 13/5 12/4 11/3 10/2 9/1 8/0 1996 Oct 09 REGISTER FUNCTION ADDRESS (HEX) IRPT 0x0000- R/W Philips Semiconductors flt7_irp IRPT_ MASK 0x0001- R/W IRPT_ STATUS 0x0002- R flt7_stat DVB compliant descrambler CHIP_ IDENTIFICATION 0x0003- R IRPT_ STATUS_ FLT14-17 0x0004- R EMPTY 0x0005 to 0x00FF 20 PRS_INP CTRL 0x0100- W EMPTY 0x0101 to 0x01FF PID0, CWPI0 0x0200- W PID1, CWPI1 0x0201- W PID2, CWPI2 0x0202- W PID3, CWPI3 0x0203- W PID4, CWPI4 0x0204- W Product specification SAA7206H PID5, CWPI5 0x0205- W REGISTER FUNCTION 15/7 - - PID5_ is_pes - ts_sc_ pid5_1 ts_sc_ pid1_1 pes_sc_ pid5_1 pes_sc_ pid1_1 pid5_ msk11 pid5_ msk3 - - - - flt11_frd flt3_frd - hadr0_3 - hadr1_4 - hadr2_4 - hadr3_5 - hadr3_4 - hadr1_3 - hadr2_3 - hadr3_3 - - - - flt10_frd flt2_frd - hadr0_2 - hadr1_2 - hadr2_2 - hadr3_2 pid5_ msk2 pid5_ msk10 pid5_ msk9 pid5_ msk1 - - - flt17_frd flt9_frd flt1_frd - hadr0_1 - hadr1_1 - hadr2_1 - hadr3_1 pes_sc_ pid1_0 pes_sc_ pid0_1 pes_sc_ pid5_0 pes_sc_ pid4_1 ts_sc_ pid1_0 ts_sc_ pid0_1 ts_sc_ pid0_0 pes_sc_ pid4_0 pes_sc_ pid0_0 pid5_ msk8 pid5_ msk0 - - - flt16_frd flt8_frd flt0_frd - hadr0_0 - hadr1_0 - hadr2_0 - hadr3_0 ts_sc_ pid5_0 ts_sc_ pid4_1 ts_sc_ pid4_0 ts_sc_ pid3_0 - pes_sc_ pid3_0 - pid5_ msk12 pid5_ msk4 - - - - flt12_frd flt4_frd - hadr0_4 pid5_ msk6 - - - - flt14_frd flt6_frd - hadr0_6 - hadr1_6 - hadr2_6 - hadr3_6 - hadr2_5 hadr1_5 - hadr0_5 - flt5_frd flt13_frd - - - - pid5_ msk5 - pes_sc_ pid2_1 pes_sc_ pid2_0 - - ts_sc_ pid2_1 ts_sc_ pid2_0 - - PID4_ is_pes PID3_ is_pes PID2_ is_pes PID1_ is_pes PID0_ is_pes DCW_valid - - - - - - - - 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 - DCW_ VALID 0x0206- W Philips Semiconductors TS_SCR_ CTRL 0x0207- R ts_sc_ pid3_1 PES_SCR_CTRL 0x0208- R DVB compliant descrambler pes_sc_ pid3_1 - pid5_ msk7 - - - - PID5_MASK 0x0209- W EMPTY 21 0x0210 to 0x02FF FLT17-16 FIRED STATUS 0x0300- R FLT15-0 FIRED STATUS 0x0301- R flt15_frd flt7_frd FLT0 STATUS 0x0302- R section to_long hadr0_7 FLT1 STATUS 0x0303- R section to_long hadr1_7 FLT2 STATUS 0x0304- R section to_long hadr2_7 SAA7206H FLT3 STATUS 0x0305- R section to_long Product specification hadr3_7 REGISTER FUNCTION 15/7 - hadr4_6 - hadr5_6 - hadr6_6 - hadr7_6 - hadr8_6 - hadr9_6 - hadr10_6 - hadr11 _6 - hadr12_6 - hadr13_6 - hadr13_5 hadr12_5 - hadr11 _5 hadr11 _4 - hadr12_4 - hadr13_4 - - hadr10_5 hadr10_4 - - - hadr10_3 - hadr11 _3 - hadr12_3 - hadr13_3 hadr9_5 hadr9_4 hadr9_3 - - - - hadr9_2 - hadr10_2 - hadr11 _2 - hadr12_2 - hadr13_2 hadr8_5 hadr8_4 hadr8_3 hadr8_2 - - - - hadr7_5 hadr7_4 hadr7_3 hadr7_2 - - - - - hadr7_1 - hadr8_1 - hadr9_1 - hadr10_1 - hadr11 _1 - hadr12_1 - hadr13_1 hadr6_5 hadr6_4 hadr6_3 hadr6_2 hadr6_1 - - - - - - hadr6_0 - hadr7_0 - hadr8_0 - hadr9_0 - hadr10_0 - hadr11 _0 - hadr12_0 - hadr13_0 hadr5_5 hadr5_4 hadr5_3 hadr5_2 hadr5_1 hadr5_0 - - - - - - hadr4_5 hadr4_4 hadr4_3 hadr4_2 hadr4_1 hadr4_0 - - - - - - 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 FLT4 STATUS 0x0306- R section to_long hadr4_7 Philips Semiconductors FLT5 STATUS 0x0307- R section to_long hadr5_7 FLT6 STATUS 0x0308- R section to_long hadr6_7 DVB compliant descrambler FLT7 STATUS 0x0309- R section to_long hadr7_7 FLT8 STATUS 0x030A- R section to_long hadr8_7 22 FLT9 STATUS 0x030B- R section to_long hadr9_7 FLT10 STATUS 0x030C- R section to_long hadr10_7 FLT11 STATUS 0x030D- R section to_long hadr11 _7 FLT12 STATUS 0x030E- R section to_long hadr12_7 FLT13 STATUS 0x030F- R section to_long Product specification SAA7206H hadr13_7 REGISTER FUNCTION 15/7 - hadr14_6 - hadr15_6 - hadr16_6 - hadr17_6 - - rst_bf14 rst_bf6 equal_cond pid6 msk6 tblid_6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk5 adr5 msk5 adr5 adr5 msk5 adr5 msk5 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 adr5 adr4 msk5 msk4 tblid_5 tblid_4 msk5 msk4 msk3 tblid_3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 pid5 pid4 pid3 enable pid12 pid11 rst_bf5 rst_bf4 rst_bf3 rst_bf13 rst_bf12 rst_bf11 rst_bf10 rst_bf2 pid10 pid2 msk2 tblid_2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 - - - - - - - - hadr17_5 hadr17_4 hadr17_3 hadr17_2 - - - - - hadr17_1 - rst_bf17 rst_bf9 rst_bf1 pid9 pid1 msk1 tblid_1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 hadr16_5 hadr16_4 hadr16_3 hadr16_2 hadr16_1 - - - - - - hadr16_0 - hadr17_0 - rst_bf16 rst_bf8 rst_bf0 pid8 pid0 msk0 tblid_0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 hadr15_5 hadr15_4 hadr15_3 hadr15_2 hadr15_1 hadr15_0 - - - - - - hadr14_5 hadr14_4 hadr14_3 hadr14_2 hadr14_1 hadr14_0 - - - - - - 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 FLT14 STATUS 0x0310- R section to_long hadr14_7 Philips Semiconductors FLT15 STATUS 0x0311- R section to_long hadr15_7 FLT16 STATUS 0x0312- R section to_long hadr16_7 DVB compliant descrambler FLT17 STATUS 0x0313- R section to_long - - hadr17_7 RESET BUFFER 16 and 17 0x0314- W RESET BUFFER 0 to 15 - pid7 msk7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 0x0315- W rst_bf15 23 rst_bf7 FLT0 CNTRL 0x0316- W FLT0 TBL_ID 0x0317- W tblid_7 FLT0 ADR BYTE0 0x0318- W FLT0 ADR BYTE1 0x0319- W FLT0 ADR BYTE2 0x031A- W FLT0 ADR BYTE3 0x031B- W Product specification SAA7206H FLT0 ADR BYTE4 0x031C- W REGISTER FUNCTION 15/7 msk7 adr7 msk7 adr7 - equal_cond pid6 msk6 tblid_6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 equal_cond pid6 msk6 tblid_6 msk6 adr6 msk6 adr6 tblid_5 msk5 adr5 msk5 adr5 msk5 pid5 enable adr5 adr4 pid12 pid4 msk4 tblid_4 msk4 adr4 msk4 adr4 msk5 msk4 adr5 adr4 msk5 msk4 adr5 adr4 adr3 msk3 adr3 msk3 adr3 pid11 pid3 msk3 tblid_3 msk3 adr3 msk3 adr3 msk5 msk4 msk3 adr5 adr4 adr3 msk5 msk4 msk3 adr5 adr4 adr3 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 pid10 pid2 msk2 tblid_2 msk2 adr2 msk2 adr2 msk5 msk4 msk3 msk2 adr5 adr4 adr3 adr2 msk5 msk4 msk3 msk2 adr5 adr4 adr3 adr2 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 pid9 pid1 msk1 tblid_1 msk1 adr1 msk1 adr1 msk5 msk4 msk3 msk2 msk1 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 msk5 msk4 msk3 msk2 msk1 pid5 pid4 pid3 pid2 pid1 pid0 msk0 tblid_0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 pid8 pid0 msk0 tblid_0 msk0 adr0 msk0 adr0 enable pid12 pid11 pid10 pid9 pid8 pid7 msk7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 - pid7 msk7 msk7 adr7 msk7 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 FLT0 ADR BYTE5 0x031D- W Philips Semiconductors FLT0 ADR BYTE6 0x031E- W FLT1 CNTRL 0x031F- W FLT1 TBL_ID 0x0320- W tblid_7 DVB compliant descrambler FLT1 ADR BYTE0 0x0321- W FLT1 ADR BYTE1 0x0322- W FLT1 ADR BYTE2 0x0323- W 24 FLT1 ADR BYTE3 0x0324- W FLT1 ADR BYTE4 0x0325- W FLT1 ADR BYTE5 0x0326- W FLT1 ADR BYTE6 0x0327- W FLT2 CNTRL 0x0328- W FLT2 TBL_ID 0x0329- W tblid_7 FLT2 ADR BYTE0 0x032A- W Product specification SAA7206H FLT2 ADR BYTE1 0x032B- W REGISTER FUNCTION 15/7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 - equal_cond pid6 msk6 tblid_6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 equal_cond pid6 adr5 msk5 adr5 enable pid5 msk5 adr5 msk5 adr5 adr4 msk4 adr4 msk4 adr4 msk4 adr4 pid12 pid4 msk5 msk4 adr5 adr4 msk5 msk4 adr5 adr4 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 pid11 pid3 msk5 msk4 msk3 adr5 adr4 adr3 msk5 msk4 msk3 tblid_5 tblid_4 tblid_3 tblid_2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 pid10 pid2 msk5 msk4 msk3 msk2 pid5 pid4 pid3 pid2 enable pid12 pid11 pid10 pid7 msk7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 - pid7 adr6 adr5 adr4 adr3 adr2 adr1 pid9 pid1 msk1 tblid_1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 pid9 pid1 msk6 msk5 msk4 msk3 msk2 msk1 adr6 adr5 adr4 adr3 adr2 adr1 msk6 msk5 msk4 msk3 msk2 msk1 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk0 adr0 msk0 adr0 pid8 pid0 msk0 tblid_0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 pid8 pid0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 FLT2 ADR BYTE2 0x032C- W Philips Semiconductors FLT2 ADR BYTE3 0x032D- W FLT2 ADR BYTE4 0x032E- W FLT2 ADR BYTE5 0x032F- W DVB compliant descrambler FLT2 ADR BYTE6 0x0330- W FLT3 CNTRL 0x0331- W FLT3 TBL_ID 0x0332- W tblid_7 25 FLT3 ADR BYTE0 0x0333- W FLT3 ADR BYTE1 0x0334- W FLT3 ADR BYTE2 0x0335- W FLT3 ADR BYTE3 0x0336- W FLT3 ADR BYTE4 0x0337- W FLT3 ADR BYTE5 0x0338- W FLT3 DR BYTE6 0x0339- W Product specification SAA7206H FLT4 CNTRL 0x033A- W REGISTER FUNCTION 15/7 msk7 tblid_6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 equal_cond pid6 msk6 tblid_6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk5 msk4 tblid_5 tblid_4 msk5 msk4 pid5 pid4 pid3 msk3 tblid_3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 enable pid12 pid11 adr5 adr4 adr3 msk5 msk4 msk3 adr5 adr4 adr3 adr2 msk2 adr2 pid10 pid2 msk2 tblid_2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk5 msk4 msk3 msk2 adr5 adr4 adr3 adr2 msk5 msk4 msk3 msk2 adr5 adr4 adr3 adr2 adr1 msk1 adr1 msk1 adr1 msk1 adr1 pid9 pid1 msk1 tblid_1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk5 msk4 msk3 msk2 msk1 adr5 adr4 adr3 adr2 adr1 msk5 msk4 msk3 msk2 msk1 adr5 adr4 adr3 adr2 adr1 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 pid8 pid0 msk0 tblid_0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk5 msk4 msk3 msk2 msk1 msk0 adr5 adr4 adr3 adr2 adr1 adr0 msk5 msk4 msk3 msk2 msk1 msk0 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 - pid7 msk7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 FLT4 TBL_ID 0x033B- W tblid_7 Philips Semiconductors FLT4 ADR BYTE0 0x033C- W FLT4 ADR BYTE1 0x033D- W FLT4 ADR BYTE2 0x033E- W DVB compliant descrambler FLT4 ADR BYTE3 0x033F- W FLT4 ADR BYTE4 0x0340- W FLT4 ADR BYTE5 0x0341- W 26 FLT4 ADR BYTE6 0x0342- W FLT5 CNTRL 0x0343- W FLT5 TBL_ID 0x0344- W tblid_7 FLT5 ADR BYTE0 0x0345- W FLT5 ADR BYTE1 0x0346- W FLT5 ADR BYTE2 0x0347- W FLT5 ADR BYTE3 0x0348- W Product specification SAA7206H FLT5 ADR BYTE4 0x0349- W REGISTER FUNCTION 15/7 msk7 adr7 msk7 adr7 - equal_cond pid6 msk6 tblid_6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 equal_cond pid6 msk6 tblid_6 msk6 adr6 msk6 adr6 tblid_5 msk5 adr5 msk5 adr5 msk5 pid5 enable adr5 adr4 pid12 pid4 msk4 tblid_4 msk4 adr4 msk4 adr4 msk5 msk4 adr5 adr4 msk5 msk4 adr5 adr4 adr3 msk3 adr3 msk3 adr3 pid11 pid3 msk3 tblid_3 msk3 adr3 msk3 adr3 msk5 msk4 msk3 adr5 adr4 adr3 msk5 msk4 msk3 adr5 adr4 adr3 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 pid10 pid2 msk2 tblid_2 msk2 adr2 msk2 adr2 msk5 msk4 msk3 msk2 adr5 adr4 adr3 adr2 msk5 msk4 msk3 msk2 adr5 adr4 adr3 adr2 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 pid9 pid1 msk1 tblid_1 msk1 adr1 msk1 adr1 msk5 msk4 msk3 msk2 msk1 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 msk5 msk4 msk3 msk2 msk1 pid5 pid4 pid3 pid2 pid1 pid0 msk0 tblid_0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 pid8 pid0 msk0 tblid_0 msk0 adr0 msk0 adr0 enable pid12 pid11 pid10 pid9 pid8 pid7 msk7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 - pid7 msk7 msk7 adr7 msk7 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 FLT5 ADR BYTE5 0x034A- W Philips Semiconductors FLT5 ADR BYTE6 0x034B- W FLT6 CNTRL 0x034C- W FLT6 TBL_ID 0x034D- W tblid_7 DVB compliant descrambler FLT6 ADR BYTE0 0x034E- W FLT6 ADR BYTE1 0x034F- W FLT6 ADR BYTE2 0x0350- W 27 FLT6 ADR BYTE3 0x0351- W FLT6 ADR BYTE4 0x0352- W FLT6 ADR BYTE5 0x0353- W FLT6 ADR BYTE6 0x0354- W FLT7 CNTRL 0x0355- W FLT7 TBL_ID 0x0356- W tblid_7 FLT7 ADR BYTE0 0x0357- W Product specification SAA7206H FLT7 ADR BYTE1 0x0358- W REGISTER FUNCTION 15/7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 - equal_cond pid6 msk6 tblid_6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 equal_cond pid6 adr5 msk5 adr5 enable pid5 msk5 adr5 msk5 adr5 adr4 msk4 adr4 msk4 adr4 msk4 adr4 pid12 pid4 msk5 msk4 adr5 adr4 msk5 msk4 adr5 adr4 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 pid11 pid3 msk5 msk4 msk3 adr5 adr4 adr3 msk5 msk4 msk3 tblid_5 tblid_4 tblid_3 tblid_2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 pid10 pid2 msk5 msk4 msk3 msk2 pid5 pid4 pid3 pid2 enable pid12 pid11 pid10 pid7 msk7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 - pid7 adr6 adr5 adr4 adr3 adr2 adr1 pid9 pid1 msk1 tblid_1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 pid9 pid1 msk6 msk5 msk4 msk3 msk2 msk1 adr6 adr5 adr4 adr3 adr2 adr1 msk6 msk5 msk4 msk3 msk2 msk1 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk0 adr0 msk0 adr0 pid8 pid0 msk0 tblid_0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 pid8 pid0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 FLT7 ADR BYTE2 0x0359- W Philips Semiconductors FLT7 ADR BYTE3 0x035A- W FLT7 ADR BYTE4 0x035B- W FLT7 ADR BYTE5 0x035C- W DVB compliant descrambler FLT7 ADR BYTE6 0x035D- W FLT8 CNTRL 0x035E- W FLT8 TBL_ID 0x031F- W tblid_7 28 FLT8 ADR BYTE0 0x0360- W FLT8 ADR BYTE1 0x0361- W FLT8 ADR BYTE2 0x0362- W FLT8 ADR BYTE3 0x0363- W FLT8 ADR BYTE4 0x0364- W FLT8 ADR BYTE5 0x0365- W FLT8 ADR BYTE6 0x0366- W Product specification SAA7206H FLT9 CNTRL 0x0367- W REGISTER FUNCTION 15/7 msk7 tblid_6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 equal_cond pid6 msk6 tblid_6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk5 msk4 tblid_5 tblid_4 msk5 msk4 pid5 pid4 pid3 msk3 tblid_3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 enable pid12 pid11 adr5 adr4 adr3 msk5 msk4 msk3 adr5 adr4 adr3 adr2 msk2 adr2 pid10 pid2 msk2 tblid_2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk5 msk4 msk3 msk2 adr5 adr4 adr3 adr2 msk5 msk4 msk3 msk2 adr5 adr4 adr3 adr2 adr1 msk1 adr1 msk1 adr1 msk1 adr1 pid9 pid1 msk1 tblid_1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk5 msk4 msk3 msk2 msk1 adr5 adr4 adr3 adr2 adr1 msk5 msk4 msk3 msk2 msk1 adr5 adr4 adr3 adr2 adr1 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 pid8 pid0 msk0 tblid_0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk5 msk4 msk3 msk2 msk1 msk0 adr5 adr4 adr3 adr2 adr1 adr0 msk5 msk4 msk3 msk2 msk1 msk0 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 - pid7 msk7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 FLT9 TBL_ID 0x0368- W tblid_7 Philips Semiconductors FLT9 ADR BYTE0 0x0369- W FLT9 ADR BYTE1 0x036A- W FLT9 ADR BYTE2 0x036B- W DVB compliant descrambler FLT9 ADR BYTE3 0x036C- W FLT9 ADR BYTE4 0x036D- W FLT9 ADR BYTE5 0x036E- W 29 FLT9 ADR BYTE6 0x0363F- W FLT10 CNTRL 0x0370- W FLT10 TBL_ID 0x0371- W tblid_7 FLT10 ADR BYTE0 0x0372- W FLT10 ADR BYTE1 0x0373- W FLT10 ADR BYTE2 0x0374- W FLT10 ADR BYTE3 0x0375- W Product specification SAA7206H FLT10 ADR BYTE4 0x0376- W REGISTER FUNCTION 15/7 msk7 adr7 msk7 adr7 - equal_cond pid6 msk6 tblid_6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 equal_cond pid6 msk6 tblid_6 msk6 adr6 msk6 adr6 tblid_5 msk5 adr5 msk5 adr5 msk5 pid5 enable adr5 adr4 pid12 pid4 msk4 tblid_4 msk4 adr4 msk4 adr4 msk5 msk4 adr5 adr4 msk5 msk4 adr5 adr4 adr3 msk3 adr3 msk3 adr3 pid11 pid3 msk3 tblid_3 msk3 adr3 msk3 adr3 msk5 msk4 msk3 adr5 adr4 adr3 msk5 msk4 msk3 adr5 adr4 adr3 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 pid10 pid2 msk2 tblid_2 msk2 adr2 msk2 adr2 msk5 msk4 msk3 msk2 adr5 adr4 adr3 adr2 msk5 msk4 msk3 msk2 adr5 adr4 adr3 adr2 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 pid9 pid1 msk1 tblid_1 msk1 adr1 msk1 adr1 msk5 msk4 msk3 msk2 msk1 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 msk5 msk4 msk3 msk2 msk1 pid5 pid4 pid3 pid2 pid1 pid0 msk0 tblid_0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 pid8 pid0 msk0 tblid_0 msk0 adr0 msk0 adr0 enable pid12 pid11 pid10 pid9 pid8 pid7 msk7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 - pid7 msk7 msk7 adr7 msk7 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 FLT10 ADR BYTE5 0x0377- W Philips Semiconductors FLT10 ADR BYTE6 0x0378- W FLT11 CNTRL 0x0379- W FLT11 TBL_ID 0x037A- W tblid_7 DVB compliant descrambler FLT11 ADR BYTE0 0x037B- W FLT11 ADR BYTE1 0x037C- W FLT11 ADR BYTE2 0x037D- W 30 FLT11 ADR BYTE3 0x037E- W FLT11 ADR BYTE4 0x037F- W FLT11 ADR BYTE5 0x0380- W FLT11 ADR BYTE6 0x0381- W FLT12 CNTRL 0x0382- W FLT12 TBL_ID 0x0383- W tblid_7 FLT12 ADR BYTE0 0x0384- W Product specification SAA7206H FLT12 ADR BYTE1 0x0385- W REGISTER FUNCTION 15/7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 - equal_cond pid6 msk6 tblid_6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 equal_cond pid6 adr5 msk5 adr5 enable pid5 msk5 adr5 msk5 adr5 adr4 msk4 adr4 msk4 adr4 msk4 adr4 pid12 pid4 msk5 msk4 adr5 adr4 msk5 msk4 adr5 adr4 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 pid11 pid3 msk5 msk4 msk3 adr5 adr4 adr3 msk5 msk4 msk3 tblid_5 tblid_4 tblid_3 tblid_2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 pid10 pid2 msk5 msk4 msk3 msk2 pid5 pid4 pid3 pid2 enable pid12 pid11 pid10 pid7 msk7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 - pid7 adr6 adr5 adr4 adr3 adr2 adr1 pid9 pid1 msk1 tblid_1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 pid9 pid1 msk6 msk5 msk4 msk3 msk2 msk1 adr6 adr5 adr4 adr3 adr2 adr1 msk6 msk5 msk4 msk3 msk2 msk1 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk0 adr0 msk0 adr0 pid8 pid0 msk0 tblid_0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 pid8 pid0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 FLT12 ADR BYTE2 0x0386- W Philips Semiconductors FLT12 ADR BYTE3 0x0387- W FLT12 ADR BYTE4 0x0388- W FLT12 ADR BYTE5 0x0389- W DVB compliant descrambler FLT12 ADR BYTE6 0x038A- W FLT13 CNTRL 0x038B- W FLT13 TBL_ID 0x038C- W tblid_7 31 FLT13 ADR BYTE0 0x038D- W FLT13 ADR BYTE1 0x038E- W FLT13 ADR BYTE2 0x038F- W FLT13 ADR BYTE3 0x0390- W FLT13 ADR BYTE4 0x0391- W FLT13 ADR BYTE5 0x0392- W FLT13 ADR BYTE6 0x0393- W Product specification SAA7206H FLT14 CNTRL 0x0394- W REGISTER FUNCTION 15/7 msk7 tblid_6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 equal_cond pid6 msk6 tblid_6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk5 msk4 tblid_5 tblid_4 msk5 msk4 pid5 pid4 pid3 msk3 tblid_3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 enable pid12 pid11 adr5 adr4 adr3 msk5 msk4 msk3 adr5 adr4 adr3 adr2 msk2 adr2 pid10 pid2 msk2 tblid_2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk5 msk4 msk3 msk2 adr5 adr4 adr3 adr2 msk5 msk4 msk3 msk2 adr5 adr4 adr3 adr2 adr1 msk1 adr1 msk1 adr1 msk1 adr1 pid9 pid1 msk1 tblid_1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk5 msk4 msk3 msk2 msk1 adr5 adr4 adr3 adr2 adr1 msk5 msk4 msk3 msk2 msk1 adr5 adr4 adr3 adr2 adr1 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 pid8 pid0 msk0 tblid_0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk5 msk4 msk3 msk2 msk1 msk0 adr5 adr4 adr3 adr2 adr1 adr0 msk5 msk4 msk3 msk2 msk1 msk0 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 - pid7 msk7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 FLT14 TBL_ID 0x0395- W tblid_7 Philips Semiconductors FLT14 ADR BYTE0 0x0396- W FLT14 ADR BYTE1 0x0397- W FLT14 ADR BYTE2 0x0398- W DVB compliant descrambler FLT14 ADR BYTE3 0x0399- W FLT14 ADR BYTE4 0x039A- W FLT14 ADR BYTE5 0x039B- W 32 FLT14 ADR BYTE6 0x039C- W FLT15 CNTRL 0x039D- W FLT15 TBL_ID 0x039E- W tblid_7 FLT15 ADR BYTE0 0x039F- W FLT15 ADR BYTE1 0x03A0- W FLT15 ADR BYTE2 0x03A1- W FLT15 ADR BYTE3 0x03A2- W Product specification SAA7206H FLT15 ADR BYTE4 0x03A3- W REGISTER FUNCTION 15/7 msk7 adr7 msk7 adr7 - msk12 msk4 pid12 pid4 msk4 tblid_4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr5 msk5 adr5 adr4 msk4 adr4 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk3 msk2 adr3 adr2 msk3 msk2 tblid_3 tblid_2 tblid_1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk3 msk2 msk1 pid3 pid2 pid1 pid11 pid10 pid9 msk3 msk2 msk1 msk0 pid8 pid0 msk0 tblid_0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk11 msk10 msk9 msk8 msk7 - equal_cond pid6 msk6 tblid_6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 adr5 msk5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable pid7 msk7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk6 msk5 - - adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 FLT15 ADR BYTE5 0x03A4- W Philips Semiconductors FLT15 ADR BYTE6 0x03A5- W FLT16 PID MASK 0x03A6- W FLT16 CNTRL 0x03A7- W FLT16 TBL_ID 0x03A8- W DVB compliant descrambler tblid_7 FLT16 ADR BYTE0 0x03A9- W FLT16 ADR BYTE1 0x03AA- W 33 FLT16 ADR BYTE2 0x03AB- W FLT16 ADR BYTE3 0x03AC- W FLT16 ADR BYTE4 0x03AD- W FLT16 ADR BYTE5 0x03AE- W FLT16 ADR BYTE6 0x03AF- W FLT16 ADR BYTE7 0x03B0- W FLT16 ADR BYTE8 0x03B1- W Product specification SAA7206H FLT16 ADR BYTE9 0x03B2- W REGISTER FUNCTION 15/7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 - msk12 msk4 pid12 pid4 msk4 tblid_4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr5 msk5 adr5 adr4 msk4 adr4 pid3 msk3 tblid_3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 pid11 msk3 msk11 msk7 - equal_cond pid6 msk6 tblid_6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 msk6 adr6 adr5 msk5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable pid7 msk7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk6 msk5 - - adr6 adr5 adr4 adr3 adr2 msk10 msk2 pid10 pid2 msk2 tblid_2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk6 msk5 msk4 msk3 msk2 adr6 adr5 adr4 adr3 adr2 msk6 msk5 msk4 msk3 msk2 adr6 adr5 adr4 adr3 adr2 adr1 msk1 adr1 msk1 adr1 msk9 msk1 pid9 pid1 msk1 tblid_1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk6 msk5 msk4 msk3 msk2 msk1 adr6 adr5 adr4 adr3 adr2 adr1 msk6 msk5 msk4 msk3 msk2 msk1 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk8 msk0 pid8 pid0 msk0 tblid_0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 FLT16 ADR BYTE10 0x03B3- W Philips Semiconductors FLT16 ADR BYTE11 0x03B4- W FLT16 ADR BYTE12 0x03B5- W FLT16 ADR BYTE13 0x03B6- W DVB compliant descrambler FLT16 ADR BYTE14 0x03B7- W FLT16 ADR BYTE15 0x03B8- W FLT16 ADR BYTE16 0x03B9- W 34 FLT17 PID MASK 0x03BA- W FLT17 CNTRL 0x03BB- W FLT17 TBL_ID 0x03BC- W tblid_7 FLT17 ADR BYTE0 0x03BD- W FLT17 ADR BYTE1 0x03BE- W FLT17 ADR BYTE2 0x03BF- W FLT17 ADR BYTE3 0x03C0- W Product specification SAA7206H FLT17 ADR BYTE4 0x03C1- W REGISTER FUNCTION 15/7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 msk7 adr7 - - cw63 cw55 cw47 cw39 cw38 cw46 cw54 cw62 - - cw61 cw53 cw45 cw37 - - adr6 adr5 msk6 msk5 adr6 adr5 adr4 msk4 adr4 - - cw60 cw52 cw44 cw36 msk6 msk5 msk4 adr6 adr5 adr4 msk6 msk5 msk4 adr6 adr5 adr4 adr3 msk3 adr3 msk3 adr3 msk3 adr3 - - cw59 cw51 cw43 cw35 msk6 msk5 msk4 msk3 adr6 adr5 adr4 adr3 msk6 msk5 msk4 msk3 adr6 adr5 adr4 adr3 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 - - cw58 cw50 cw42 cw34 msk6 msk5 msk4 msk3 msk2 adr6 adr5 adr4 adr3 adr2 msk6 msk5 msk4 msk3 msk2 adr6 adr5 adr4 adr3 adr2 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 - - cw57 cw49 cw41 cw33 msk6 msk5 msk4 msk3 msk2 msk1 adr6 adr5 adr4 adr3 adr2 adr1 msk6 msk5 msk4 msk3 msk2 msk1 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 - - cw56 cw48 cw40 cw32 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr6 adr5 adr4 adr3 adr2 adr1 adr0 msk6 msk5 msk4 msk3 msk2 msk1 msk0 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 FLT17 ADR BYTE5 0x03C2- W Philips Semiconductors FLT17 ADR BYTE6 0x03C3- W FLT17 ADR BYTE7 0x03C4- W FLT17 ADR BYTE8 0x03C5- W DVB compliant descrambler FLT17 ADR BYTE9 0x03C6- W FLT17 ADR BYTE10 0x03C7- W FLT17 ADR BYTE11 0x03C8- W 35 FLT17 ADR BYTE12 0x03C9- W FLT17 ADR BYTE13 0x03CA- W FLT17 ADR BYTE14 0x03CB- W FLT17 ADR BYTE15 0x03CC- W FLT17 ADR BYTE16 0x03CD- W EMPTY 0x03CE to 0x0FFF CTRL WRD0_ EVEN3 0x1000- W Product specification SAA7206H CTRL_ WRD0_ EVEN2 0x1001- W REGISTER FUNCTION 15/7 cw31 cw23 cw15 cw7 cw63 cw55 cw47 cw39 cw31 cw23 cw15 cw7 cw63 cw55 cw47 cw39 cw31 cw23 cw15 cw7 cw63 cw55 cw47 cw39 cw31 cw23 cw15 cw7 cw63 cw55 cw54 cw62 cw6 cw14 cw22 cw21 cw13 cw5 cw61 cw53 cw30 cw29 cw38 cw37 cw46 cw45 cw54 cw53 cw52 cw44 cw36 cw28 cw20 cw12 cw4 cw60 cw52 cw62 cw61 cw60 cw6 cw5 cw4 cw14 cw13 cw12 cw22 cw21 cw20 cw19 cw11 cw3 cw59 cw51 cw43 cw35 cw27 cw19 cw11 cw3 cw59 cw51 cw30 cw29 cw28 cw27 cw38 cw37 cw36 cw35 cw46 cw45 cw44 cw43 cw54 cw53 cw52 cw51 cw50 cw42 cw34 cw26 cw18 cw10 cw2 cw58 cw50 cw42 cw34 cw26 cw18 cw10 cw2 cw58 cw50 cw62 cw61 cw60 cw59 cw58 cw6 cw5 cw4 cw3 cw2 cw14 cw13 cw12 cw11 cw10 cw22 cw21 cw20 cw19 cw18 cw17 cw9 cw1 cw57 cw49 cw41 cw33 cw25 cw17 cw9 cw1 cw57 cw49 cw41 cw33 cw25 cw17 cw9 cw1 cw57 cw49 cw30 cw29 cw28 cw27 cw26 cw25 cw38 cw37 cw36 cw35 cw34 cw33 cw46 cw45 cw44 cw43 cw42 cw41 cw54 cw53 cw52 cw51 cw50 cw49 cw48 cw40 cw32 cw24 cw16 cw8 cw0 cw56 cw48 cw40 cw32 cw24 cw16 cw8 cw0 cw56 cw48 cw40 cw32 cw24 cw16 cw8 cw0 cw56 cw48 cw62 cw61 cw60 cw59 cw58 cw57 cw56 cw6 cw5 cw4 cw3 cw2 cw1 cw0 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw22 cw21 cw20 cw19 cw18 cw17 cw16 cw30 cw29 cw28 cw27 cw26 cw25 cw24 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 CTRL WRD0_ EVEN1 0x1002- W Philips Semiconductors CTRL_ WRD0_ EVEN0 0x1003- W CTRL WRD0_ ODD3 0x1004- W CTRL_ WRD0_ ODD2 0x1005- W DVB compliant descrambler CTRL WRD0_ ODD1 0x1006- W CTRL_ WRD0_ ODD0 0x1007- W CTRL WRD1_ EVEN3 0x1008- W 36 CTRL_ WRD1_ EVEN2 0x1009- W CTRL WRD1_ EVEN1 0x100A- W CTRL_ WRD1_ EVEN0 0x100B- W CTRL WRD1_ ODD3 0x100C- W CTRL_ WRD1_ ODD2 0x100D- W CTRL WRD1_ ODD1 0x100E- W CTRL_ WRD1_ ODD0 0x100F- W Product specification SAA7206H CTRL WRD2_ EVEN3 0x1010- W REGISTER FUNCTION 15/7 cw47 cw39 cw31 cw23 cw15 cw7 cw63 cw55 cw47 cw39 cw31 cw23 cw15 cw7 cw63 cw55 cw47 cw39 cw31 cw23 cw15 cw7 cw63 cw55 cw47 cw39 cw31 cw23 cw15 cw7 cw6 cw14 cw22 cw30 cw38 cw37 cw29 cw21 cw13 cw5 cw46 cw45 cw54 cw53 cw62 cw61 cw6 cw5 cw4 cw60 cw52 cw44 cw36 cw28 cw20 cw12 cw4 cw14 cw13 cw12 cw22 cw21 cw20 cw30 cw29 cw28 cw38 cw37 cw36 cw35 cw27 cw19 cw11 cw3 cw59 cw51 cw43 cw35 cw27 cw19 cw11 cw3 cw46 cw45 cw44 cw43 cw54 cw53 cw52 cw51 cw62 cw61 cw60 cw59 cw6 cw5 cw4 cw3 cw2 cw58 cw50 cw42 cw34 cw26 cw18 cw10 cw2 cw58 cw50 cw42 cw34 cw26 scw18 cw10 cw2 cw14 cw13 cw12 cw11 cw10 cw22 cw21 cw20 cw19 cw18 cw30 cw29 cw28 cw27 cw26 cw38 cw37 cw36 cw35 cw34 cw33 cw25 cw17 cw9 cw1 cw57 cw49 cw41 cw33 cw25 cw17 cw9 cw1 cw57 cw49 cw41 cw33 cw25 cw17 cw9 cw1 cw46 cw45 cw44 cw43 cw42 cw41 cw54 cw53 cw52 cw51 cw50 cw49 cw62 cw61 cw60 cw59 cw58 cw57 cw6 cw5 cw4 cw3 cw2 cw1 cw0 cw56 cw48 cw40 cw32 cw24 cw16 cw8 cw0 cw56 cw48 cw40 cw32 cw24 cw16 cw8 cw0 cw56 cw48 cw40 cw32 cw24 cw16 cw8 cw0 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw22 cw21 cw20 cw19 cw18 cw17 cw16 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw38 cw37 cw36 cw35 cw34 cw33 cw32 cw46 cw45 cw44 cw43 cw42 cw41 cw40 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 CTRL_ WRD2_ EVEN2 0x1011- W Philips Semiconductors CTRL WRD2_ EVEN1 0x1012- W CTRL_ WRD2_ EVEN0 0x1013- W CTRL WRD2_ ODD3 0x1014- W DVB compliant descrambler CTRL_ WRD2_ ODD2 0x1015- W CTRL WRD2_ ODD1 0x1016- W CTRL_ WRD2_ ODD0 0x1017- W 37 CTRL WRD3_ EVEN3 0x1018- W CTRL_ WRD3_ EVEN2 0x1019- W CTRL WRD3_ EVEN1 0x101A- W CTRL_ WRD3_ EVEN0 0x101B- W CTRL WRD3_ ODD3 0x101C- W CTRL_ WRD3_ ODD2 0x101D- W CTRL WRD3_ ODD1 0x101E- W Product specification SAA7206H CTRL_ WRD3_ ODD0 0x101F- W REGISTER FUNCTION 15/7 cw63 cw55 cw47 cw39 cw31 cw23 cw15 cw7 cw63 cw55 cw47 cw39 cw31 cw23 cw15 cw7 cw63 cw55 cw47 cw39 cw31 cw23 cw15 cw7 cw63 cw55 cw47 cw39 cw31 cw23 cw22 cw30 cw38 cw46 cw54 cw53 cw45 cw37 cw29 cw21 cw62 cw61 cw6 cw5 cw14 cw13 cw22 cw21 cw20 cw12 cw4 cw60 cw52 cw44 cw36 cw28 cw20 cw30 cw29 cw28 cw38 cw37 cw36 cw46 cw45 cw44 cw54 cw53 cw52 cw51 cw43 cw35 cw27 cw19 cw11 cw3 cw59 cw51 cw43 cw35 cw27 cw19 cw62 cw61 cw60 cw59 cw6 cw5 cw4 cw3 cw14 cw13 cw12 cw11 cw22 cw21 cw20 cw19 cw18 cw10 cw2 cw58 cw50 cw42 cw34 cw26 cw18 cw10 cw2 cw58 cw50 cw42 cw34 cw26 cw18 cw30 cw29 cw28 cw27 cw26 cw38 cw37 cw36 cw35 cw34 cw46 cw45 cw44 cw43 cw42 cw54 cw53 cw52 cw51 cw50 cw49 cw41 cw33 cw25 cw17 cw9 cw1 cw57 cw49 cw41 cw33 cw25 cw17 cw9 cw1 cw57 cw49 cw41 cw33 cw25 cw17 cw62 cw61 cw60 cw59 cw58 cw57 cw6 cw5 cw4 cw3 cw2 cw1 cw14 cw13 cw12 cw11 cw10 cw9 cw22 cw21 cw20 cw19 cw18 cw17 cw16 cw8 cw0 cw56 cw48 cw40 cw32 cw24 cw16 cw8 cw0 cw56 cw48 cw40 cw32 cw24 cw16 cw8 cw0 cw56 cw48 cw40 cw32 cw24 cw16 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw38 cw37 cw36 cw35 cw34 cw33 cw32 cw46 cw45 cw44 cw43 cw42 cw41 cw40 cw54 cw53 cw52 cw51 cw50 cw49 cw48 cw62 cw61 cw60 cw59 cw58 cw57 cw56 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 CTRL WRD4_ EVEN3 0x1020- W Philips Semiconductors CTRL_ WRD4_ EVEN2 0x1021- W CTRL WRD4_ EVEN1 0x1022- W CTRL_ WRD4_ EVEN0 0x1023- W DVB compliant descrambler CTRL WRD4_ ODD3 0x1024- W CTRL_ WRD4_ ODD2 0x1025- W CTRL WRD4_ ODD1 0x1026- W 38 CTRL_ WRD4_ ODD0 0x1027- W CTRL WRD5_ EVEN3 0x1028- W CTRL_ WRD5_ EVEN2 0x1029- W CTRL WRD5_ EVEN1 0x102A- W CTRL_ WRD5_ EVEN0 0x102B- W CTRL WRD5_ ODD3 0x102C- W CTRL_ WRD5_ ODD2 0x102D- W Product specification SAA7206H CTRL WRD5_ ODD1 0x102E- W REGISTER FUNCTION 15/7 cw15 cw7 cw63 cw55 cw47 cw39 cw31 cw23 cw15 cw7 - - data14 data6 - - data14 data6 - - data14 data6 - - data14 data6 - - data14 data6 - - data13 data5 data5 data13 - - - - data12 data4 - - data12 data4 data5 data4 data13 data12 - - - - - - data11 data3 - - data11 data3 - - data11 data3 data5 data4 data3 data13 data12 data11 - - - - - - - - data10 data2 - - data10 data2 - - data10 data2 - - data10 data2 data5 data4 data3 data2 data13 data12 data11 data10 data7 - - data7 - - data7 - - data7 - - data7 - - - - - - - - - - - - data9 data1 - - data9 data1 - - data9 data1 - - data9 data1 - - data9 data1 cw6 cw5 cw4 cw3 cw2 cw1 cw14 cw13 cw12 cw11 cw10 cw9 cw22 cw21 cw20 cw19 cw18 cw17 cw30 cw29 cw28 cw27 cw26 cw25 cw38 cw37 cw36 cw35 cw34 cw33 cw32 cw24 cw16 cw8 cw0 - - data8 data0 - - data8 data0 - - data8 data0 - - data8 data0 - - data8 data0 cw46 cw45 cw44 cw43 cw42 cw41 cw40 cw54 cw53 cw52 cw51 cw50 cw49 cw48 cw62 cw61 cw60 cw59 cw58 cw57 cw56 cw6 cw5 cw4 cw3 cw2 cw1 cw0 cw14 cw13 cw12 cw11 cw10 cw9 cw8 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 CTRL_ WRD5_ ODD0 0x102F- W Philips Semiconductors DFLT_ CTRL_ WRD3 0x1030- W DFLT_ CTRL_ WRD2 0x1031- W DFLT_ CTRL_ WRD1 0x1032- W DVB compliant descrambler DFLT_ CTRL_ WRD0 0x1033- W EMPTY 0x1034 to 0x1FFF FLT0_ BUFFER 0x2000 to 0x207F- R data15 39 EMPTY 0x2080 to 0x20FF FLT1_ BUFFER 0x2100 to 0x217F- R data15 EMPTY 0x2180 to 0x21FF FLT2_ BUFFER 0x2200 to 0x227F- R data15 EMPTY 0x2280 to 0x22FF FLT3_ BUFFER 0x2300 to 0x237F- R data15 EMPTY 0x2380 to 0x23FF Product specification SAA7206H FLT4_ BUFFER 0x2400 to 0x247F- R data15 REGISTER FUNCTION 15/7 - - data14 data6 - - data14 data6 - - data14 data6 - - data14 data6 - - data14 data6 - - data14 data6 - - data14 data6 - - - data13 data5 - - - data5 data13 - - data12 data4 - - data12 data4 - - - - data5 data4 data13 data12 - - - data11 data3 - - data11 data3 - - data11 data3 - - - - - data5 data4 data3 data13 data12 data11 - - - - data10 data2 - - data10 data2 - - data10 data2 - - data10 data2 - - - - - - data5 data4 data3 data2 data13 data12 data11 data10 - - - - - data9 data1 - - data9 data1 - - data9 data1 - - data9 data1 - - data9 data1 - - - - - - - data5 data4 data3 data2 data1 data13 data12 data11 data10 data9 - - - - - - data8 data0 - - data8 data0 - - data8 data0 - - data8 data0 - - data8 data0 - - data8 data0 - - - - - - - - data5 data4 data3 data2 data1 data0 data13 data12 data11 data10 data9 data8 data7 - - data7 - - data7 - - data7 - - data7 - - data7 - - data7 - - - - - - - - - - - - - - - - 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 EMPTY 0x2480 to 0x24FF Philips Semiconductors FLT5_ BUFFER 0x2500 to 0x257F- R data15 EMPTY 0x2580 to 0x25FF FLT6_ BUFFER 0x2600 to 0x267F- R data15 DVB compliant descrambler EMPTY 0x2680 to 0x26FF FLT7_ BUFFER 0x2700 to 0x277F- R data15 EMPTY 0x2780 to 0x27FF 40 FLT8_ BUFFER 0x2800 to 0x287F- R data15 EMPTY 0x2880 to 0x28FF FLT9_ BUFFER 0x2900 to 0x297F- R data15 EMPTY 0x2980 to 0x29FF FLT10_ BUFFER 0x2A00 0x2A7F- R data15 EMPTY 0x2A80 to 0x2AFF FLT11_ BUFFER 0x2B00 to 0x2B7F- R data15 Product specification SAA7206H EMPTY 0x2B80 to 0x2BFF REGISTER FUNCTION 15/7 data14 data6 - - data14 data6 - - data14 data6 - - data14 data6 - - data14 data6 - - data14 data6 - - - - - - data5 data4 data13 data12 - - - - - - data11 data3 - - data5 data4 data3 data13 data12 data11 - - - - - - - - data10 data2 - - data10 data2 - - data5 data4 data3 data2 data13 data12 data11 data10 - - - - - - - - - - data9 data1 - - data9 data1 - - data9 data1 - - data5 data4 data3 data2 data1 data13 data12 data11 data10 data9 - - - - - - - - - - - - data8 data0 - - data8 data0 - - data8 data0 - - data8 data0 - - data5 data4 data3 data2 data1 data0 data13 data12 data11 data10 data9 data8 - - - - - - - - - - - - data5 data4 data3 data2 data1 data0 data13 data12 data11 data10 data9 data8 data7 - - data7 - - data7 - - data7 - - data7 - - data7 - - 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ADDRESS (HEX) BITS 1996 Oct 09 FLT12_ BUFFER 0x2C00 to 0x2C7F- R data15 Philips Semiconductors EMPTY 0x2C80 to 0x2CFF FLT13_ BUFFER 0x2D00 to 0x2D7F- R data15 EMPTY 0x2D80 to 0x2DFF DVB compliant descrambler FLT14_ BUFFER 0x2E00 to 0x2E7F- R data15 EMPTY 0x2E80 to 0x2EFF FLT15_ BUFFER 0x2F00 to 0x2F7F- R data15 41 EMPTY 0x2F80 to 0x2FFF FLT16_ BUFFER 0x3000 to 0x307F- R data15 EMPTY 0x3080 to 0x30FF FLT17_ BUFFER 0x3100 to 0x317F- R data15 EMPTY 0x3180 to 0xFFFF Product specification SAA7206H Philips Semiconductors Product specification DVB compliant descrambler 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD(pads) VDDD(core) VI VO IDDD, ISSD Ii(max) Io(max) Ptot Tstg Tamb 9 PARAMETER digital supply voltage for pads (+5 V) digital supply voltage for core (+3.3 V) DC input voltage DC output voltage; DC current; VDD or VSS maximum input current maximum output current total power dissipation storage temperature operating ambient temperature MIN. -0.5 -0.5 -0.5 -0.5 - -10 -20 - -65 0 SAA7206H MAX. +6.5 +5.0 VDDD + 0.5 VDDD + 0.5 52 +10 +20 250 +150 70 V V V V mA mA mA UNIT mW C C HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. Every pin withstands the ESD test in accordance with "UZW-BO/FQ-B3020"; 0 , 200 pF Machine Model (300 V). 10 THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 56 UNIT K/W 11 DC CHARACTERISTICS VDDD(core) = 3.3 V 0.3 V; VDDD = 5 V 0.5 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL IDDD(q) IDDD(core) IDDD(pads) VIL VIH ILI VOL VOH Notes 1. All inputs at VSSD or VDDD. 2. Operating inputs, unloaded outputs. PARAMETER quiescent supply current digital operating current for core digital operating current for pads LOW level input voltage HIGH level input voltage input leakage current LOW level output voltage HIGH level output voltage Vi = 0 V; Tamb = 25 C Vi = 5.5 V; Tamb = 25 C Io = 4 mA Io = 4 mA CONDITIONS VDDD = 5.5 V; note 1 VDDD = 5.5 V; VDDD(core) = 3.6 V; note 2 VDDD = 5.5 V; VDDD(core) = 3.6 V; note 2 - - - 0 2.0 - - 0 0.9VDDD MIN. 42 10 0.8 VDDD 10 10 0.1VDDD VDDD MAX. 100 A mA mA V V A A V V UNIT 1996 Oct 09 42 Philips Semiconductors Product specification DVB compliant descrambler 12 AC CHARACTERISTICS VDDD(core) = 3.3 V 0.3 V; VDDD = 5 V 0.5 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS - note 1 111 - - 20 20 - - 15 5 - see also Fig.9 111 - - 20 20 - - 15 5 MIN. SAA7206H MAX. UNIT Input interface; (see Fig.12) Ci Tcy ti(r)(CLK) ti(f)(CLK) tCLKH tCLKL ti(r) ti(f) tsu(i) th(i) Ci Tcy(CS) tr(CS) tf(CS) tCSH tCSL ti(r) ti(f) tsu(i) th(i) tCSLr to(r) to(f) to(d) to(h) toL(Z) toH(Z) input capacitance byte strobe input cycle time (asynchronous mode) input clock rise time input clock fall time input clock HIGH time input clock LOW time input rise time input fall time input set-up time input hold time 5 - 10 10 - - 10 10 - - pF ns ns ns ns ns ns ns ns ns Microcontroller interface input capacitance chip select cycle time chip select rise time chip select fall time chip select HIGH time chip select LOW time 5 - 10 10 - - 10 10 - - - 10 10 30 - 30 30 pF ns ns ns ns ns WRITE CYCLE; (see Figs 14 and 15) input rise time input fall time input set-up time input hold time ns ns ns ns READ CYCLE; (see Fig.16) chip select LOW time in read mode output rise time output fall time output delay time output hold time output low Z time output high Z time note 2 note 2 240 - - - 5 3 3 ns ns ns ns ns ns ns 1996 Oct 09 43 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H SYMBOL PARAMETER CONDITIONS - - MIN. MAX. UNIT Output interface; (see Fig.13) Co CL Tcy(DCLK) to(r)(DCLK) to(f)(DCLK) tDCLKH tDCLKL to(r) to(f) to(h) to(d) Notes 1. In the synchronous mode all input signals are referenced to the descrambler clock which is specified in the output interface part. In the asynchronous mode all input signals are referenced to the MBCLK. 2. Data output is low impedance when both (DCS = 0) AND (R/W = 1). toL(Z) is defined after the last change of both signals which makes the data output low impedance. toH(Z) is defined after the first change of both signals which makes the data output high impedance. output capacitance output load capacitance output clock cycle time (DCLK) output clock rise time output clock fall time output clock HIGH time output clock LOW time output rise time output fall time output hold time output delay time CL = 5 pF CL = 30 pF 10 50 - 10 10 - - 10 10 - 40 pF pF ns ns ns ns ns ns ns ns ns 111 - - 20 20 - - 3 - 1996 Oct 09 44 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H handbook, full pagewidth ti(r)(CLK) tCLKH ti(f)(CLK) tCLKL MBCLK (asynchronous mode) or DCS (synchronous mode) Tcy(CLK) tsu(i) MIN 7 to MIN0 MDV MB/MB MSYNC ti(r) ti(f) th(i) MGG324 Fig.12 Timing definition of the input interface signals. handbook, full pagewidth to(r)(DCLK) to(f)(DCLK) tDCLKH tDCLKL DCS Tcy(DCLK) to(d) to(h) DATO7 to DATO0 DVO SYNCO to(r) to(f) MGG325 Fig.13 Timing definition of the output interface signals. 1996 Oct 09 45 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H handbook, full pagewidth tr(CS) tCSH tf(CS) tCSL DCS Tcy(CS) ti(r) ti(f) A1 tsu(i) th(i) tsu(i) th(i) A0 tsu(i) th(i) tsu(i) th(i) R/W tsu(i) th(i) tsu(i) th(i) DAT0 to DAT7 MSByte LSByte MGG326 ti(r) ti(f) Fig.14 Timing definition of the microcontroller interface signals (address write cycle). 1996 Oct 09 46 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H handbook, full pagewidth tr(CS) tCSH tf(CS) tCSL DCS Tcy(CS) ti(f) ti(r) A1 tsu(i) th(i) tsu(i) th(i) A0 tsu(i) th(i) tsu(i) th(i) R/W tsu(i) th(i) tsu(i) th(i) DAT0 to DAT7 MSByte LSByte MGG327 ti(r) ti(f) Fig.15 Timing definition of the microcontroller interface signals (data write cycle). 1996 Oct 09 47 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H handbook, full pagewidth tf(CS) DCS tCSLr tr(CS) A1 A0 tsu(i) th(i) R/W to(d) to(h) to(h) to(d) DATA MSByte LSByte toL(Z) to(r) to(f) toH(Z) MGG328 Fig.16 Timing definition of the microcontroller interface signals (read cycle). 1996 Oct 09 48 Philips Semiconductors Product specification DVB compliant descrambler 13 PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SAA7206H SOT319-2 c y X 51 52 33 32 ZE A e E HE A A2 A1 Q (A 3) Lp L detail X pin 1 index wM bp 64 1 wM D HD ZD 19 20 e bp vMA B vM B 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.4 1.2 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 1996 Oct 09 49 Philips Semiconductors Product specification DVB compliant descrambler 14 SOLDERING 14.1 Introduction SAA7206H If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). 14.3.2 SO There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 14.2 Reflow soldering Reflow soldering techniques are suitable for all QFP and SO packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Manual" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 14.3 14.3.1 Wave soldering QFP Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. 14.3.3 METHOD (QFP AND SO) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Repairing soldered joints Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 1996 Oct 09 50 Philips Semiconductors Product specification DVB compliant descrambler 15 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values SAA7206H This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Oct 09 51 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 247 9145, Fax. +7 095 247 9144 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996 Internet: http://www.semiconductors.philips.com SCA52 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1200/02/pp52 Date of release: 1996 Oct 09 Document order number: 9397 750 01331 |
Price & Availability of SAA7206
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |